Intel Launches Chip Making Technique That It Claims To Be Faster Than Its Competitors

Intel claims to make chips that are faster than its competitors. (photo credit: pixabay)

JAKARTA - A research team at Intel Corp. on Saturday, December 11 unveiled work they believe will help accelerate and continue to shrink computing chips over the next ten years. This is done with several technologies aimed at stacking parts of the chip on top of each other.

The Intel Research Components Group introduced the work in a paper at an international conference held in San Francisco. These Silicon Valley companies are working to regain their lead in making the smallest and fastest chips.

Over the past few years, they have lost out on making the fastest chips to competitors such as Taiwan Semiconductor Manufacturing Co (TMSC) and Samsung Electronics Co Ltd.

While Intel CEO Pat Gelsinger has laid out a commercial plan aimed at regaining that edge by 2025, the research work launched last Saturday provides an overview of how Intel plans to compete beyond 2025.

One way, Intel packs more computing power into chips is by stacking "tiles" or "chiplets" in three dimensions rather than making all the chips as one piece in two dimensions. Intel demonstrated work Saturday that could allow 10 times more connections between stacked tiles, meaning that more complex tiles can be stacked on top of one another.

But perhaps the biggest advance demonstrated last Saturday was a research paper showing how to stack transistors -- the tiny switches that make up the most basic building blocks of chips by representing digital logic 1s and 0s -- on top of one another.

Intel believes that the technology will result in a 30% to 50% increase in the number of transistors that can be packed into a given area of a chip. Increasing the number of transistors is the main reason why chips have consistently gotten faster over the last 50 years.

"By stacking devices directly on top of each other, we're saving area", Paul Fischer, Director and Senior Principal Engineer at Intel Components Research Group told Reuters in an interview.

"We're reducing the interconnect length and saving energy, making it not only more cost-effective but also better-performing", he said.